Modern ICs may include thousands, millions and even higher numbers of electronic devices such as transistors. As these electronic devices turn on and off in an (IC) chip, electric current flow changes in power conductors near these electronic devices. A change in current flow near the electronic devices induces voltage or power supply noise within the IC. Power supply interconnects or power conductors such as conductive layers, traces, or other conductive interconnects within the IC distribute power supply signals. Electronic devices in the IC connect to the power supply interconnects, namely power (VDD) and ground (GND) under normal operation. Power supply noise is a concern of all chip designers in modern IC or semiconductor die manufacturing design. IC designers design integrated decoupling capacitors between the power supply interconnects, namely positive supply voltage (VDD) and zero voltage potential ground (GND). Connecting decoupling capacitors between the power supply interconnects within the integrated circuit is one method to reduce power supply noise. A decoupling capacitor acts as a temporary current source to provide power when a proximate electronic device pulls power from the power supply interconnect of the IC.
IC designers may use integrated devices, such as NMOS (n-type metal oxide semiconductor) transistors to fabricate decoupling capacitors within the IC. NMOS transistors typically contain an oxide layer that provides a semiconductor path for the electrical current that the decoupling capacitor uses, namely for power supply interconnect noise reduction. The oxide layer effectively acts as a dielectric layer for the integrated decoupling capacitor. Unfortunately, oxide layers, generally made of SiO2 (silicon dioxide) are subject to shorts or high leakage currents due to manufacturing defects, degradation of the oxide layer from use, or other physical parameters which may adversely affect the oxide layer. A bad oxide layer may result in the reduction or loss of decoupling capacitance and ultimately result in decoupling capacitor failure. Designers may fabricate a larger oxide layer to accommodate more current and thus make the decoupling capacitor more immune to failure. However, the larger the oxide layer, the more real estate (useable area of the IC) that the decoupling capacitor consumes. Larger oxide layers may also require specialized fabrication processes that cause the manufacturing process to be more complex and potentially more costly. It is a challenging trade-off for designers to minimize the oxide layer size and yet attain high decoupling capacitor yield. Decoupling capacitance degradation can further reduce the performance and yield of entire integrated circuit chips and adversely affect IC manufacturing.
To reduce the impact of decoupling capacitor failure in the IC, IC designers may include the ability to disconnect or switch-out bad decoupling capacitors within the IC. One method to switch-out decoupling capacitors is with an electronic switching signal, typically a binary on/off signal. Chip designers design electronic switch circuits that connect to respective decoupling capacitors to allow for the effective electronic removal of decoupling capacitors from the overall IC. A dedicated decoupling capacitor electronic switch circuit may remove the source of either power or ground from a particular bad decoupling capacitor to effectively remove the decoupling capacitor from the power supply interconnect of the IC. However, it is not feasible in a large scale integrated circuit to employ a dedicated decoupling capacitor switch circuit and dedicated capacitor switch signal for each decoupling capacitor of the IC. Dedicated switch signals would require multiple interconnects which use up valuable IC real estate. One approach for dealing with this problem is to group a collection of decoupling capacitors together by design logic rules to reduce the number of switching signals that the group of decoupling capacitors needs for switch out on the IC. Each decoupling capacitor still has a dedicated switch, but the group of decoupling capacitors shares a common switch signal. When one switch signal toggles to a negative state, a group of decoupling capacitors switches out of the circuit. Unfortunately, to switch out one bad decoupling capacitor, this method requires switching out all of the decoupling capacitors in the group. This is a major disadvantage of this method. When the electronic switching circuitry removes a group of decoupling capacitors, the effect is an undesirable larger decrease in noise reduction ability than the removal of only the bad decoupling capacitor itself.
As the performance requirements of integrated circuit chips increase, the need for more effective integrated decoupling capacitors rises as well. One purpose of integrated decoupling capacitors is to dampen the power supply noise levels across the power supply interconnects of the integrated circuit. Degradation of the decoupling capacitors on the IC will reduce the overall noise reduction potential of the IC and can eventually result in a total loss of the integrated circuit.
What is needed is a method and apparatus that addresses the problems associated with managing integrated decoupling capacitors in integrated circuits as described above.